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[VHDL-FPGA-Verilog] ex9_cof_M4K_test1

Description: ram的Verilog实现，很不错-ram of the Verilog implementation, very good ~~~~~
Platform: | Size: 1219584 | Author: 侯勇 | Hits:

[VHDL-FPGA-Verilog] fh_ram_s_w_r_16_512

Description: 单口串行可读写16x512的ram的verilog源代码-singal serial writeable and readable 16x512 ram
Platform: | Size: 1024 | Author: liuzhe | Hits:

[VHDL-FPGA-Verilog] Abus_fifo_ram_V1

Description: 该模块是基于verilog语言编写的双口ram模块，可将该该模块作为缓存模块使用-surpost ram write/read
Platform: | Size: 1024 | Author: 杨春 | Hits:

[Algorithm] AWSEQ_RAM_RW_A_DFF

Description: Verilog AWSEQ RAM DFF Verilog code
Platform: | Size: 2048 | Author: jc | Hits:

[VHDL-FPGA-Verilog] EDA_dianzhen

Description: 使用verilog语言写的16*16的点阵，能够实现左移、右移、暂停、复位等功能，可以自己定制RAM，改变显示的内容。-Verilog language written using the 16* 16 dot matrix, to achieve left, right, pause, reset and other functions, you can customize RAM, change the display content.
Platform: | Size: 791552 | Author: 李 建 | Hits:

[VHDL-FPGA-Verilog] doublefloat_RAM

Description: 使用verilog编写的一个双浮点RAM，支持对字、字节、半字、双字的读写，包含testbench和wave.do文件-Use verilog to implement a double float RAM, supporting the read and write of halfword,byte,word,double word. It includes the testbench and wave.do
Platform: | Size: 2048 | Author: WYaode | Hits:

[VHDL-FPGA-Verilog] DDR_FLASH_VHDL_Verilog

Description: FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
Platform: | Size: 17408 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] ram_verilog

Description: 本程序用verilog实现实现了RAM读写功能-This programe describe the properties of reading and writing ram.
Platform: | Size: 320512 | Author: lipeng | Hits:

[VHDL-FPGA-Verilog] labobot_vhd

Description: descripcion de una memoria ram usando verilog
Platform: | Size: 5120 | Author: jhonyy | Hits:

[VHDL-FPGA-Verilog] writing

Description: 关于RAM/ROM的一个写操作的程序，语言为verilog-On RAM/ROM, a write operation procedures, language verilog
Platform: | Size: 1024 | Author: 刘春 | Hits:

[VHDL-FPGA-Verilog] ram_sp_ar_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] ram_sp_sr_sw.v

Description: this is a verilog source code for Single Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] ram_dp_sr_sw.v

Description: this is a verilog source code for Dual Port RAM Synchronous Read/Write.
Platform: | Size: 1024 | Author: soumojit acharyya | Hits:

[VHDL-FPGA-Verilog] dpram

Description: 包含整个工程，是用verilog来编写，实现双口ram的功能-Contains the entire project is to write Verilog to achieve the function of the dual-port ram
Platform: | Size: 2258944 | Author: ghj | Hits:

[VHDL-FPGA-Verilog] or1200_sopc

Description: 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram，最小系统soc。包括片上ram的软件系统（C语言编写）都有。但下载者要使用此系统需要很多工具链，搞soc的应该都装好了。 绝对原创！用quartusII11.0在Altera DE2-115上验证通过，Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Right?
Platform: | Size: 31982592 | Author: 咖啡猫 | Hits:

[VHDL-FPGA-Verilog] ram2x128

Description: this 2x128 ram code in verilog-this is 2x128 ram code in verilog
Platform: | Size: 2048 | Author: garggy | Hits:

[VHDL-FPGA-Verilog] dw8051-used-in-FPGA

Description: 自己下载的dw8051核，并在atlys fpga开发板上运行成功。其中rom和ram都已经生成，4个并行I/O口也有。编程语言是verilog。另外，还有hex转in文件的小软件，以及Uedit这个文本编辑器，它是用来给dw8051的rom载入程序的。-The the dw8051 nuclear, download and run atlys fpga development board. Rom and ram have been generated, there are four parallel I/O port. The programming language is verilog. In addition, there are small software to the hex turn in documents, and Uedit text editor, it is used to dw8051 rom loaded program.
Platform: | Size: 29199360 | Author: ayading826 | Hits:

[VHDL-FPGA-Verilog] dualram

Description: 本文件给出了一种双口RAM的代码，开发语言为verilog。测试可用，欢迎下载-This document gives a dual-port RAM code verilog development language. Test is available, welcome to download
Platform: | Size: 1024 | Author: 秦艳召 | Hits:

[VHDL-FPGA-Verilog] ddr-sdram

Description: It is complete document for DDR SD RAM program in verilog hdl
Platform: | Size: 897024 | Author: srikanth | Hits:

[Other] [EDACN-monthly]1

Description: Eda主要介绍的逻辑设计与集成电路：FPGA 设计的指导性原则（连载之二） 典型的FPGA 设计流程 大型复杂FPGA 设计推荐设计方式──Modular Design Coding Style 与综合前后仿真 数据接口设计 关于有限状态机编码的技巧和注意事项 做distributed ram 时遇到的几个不太明白的信号 Source Insight 兼容VHDL 与VERILOG 如何实现信号延时？ [转载]新手学习技巧-EDA introduces the logical design of integrated circuits: FPGA design of the guiding principles (Part II) Typical FPGA design flow Large, complex FPGA design recommended design approach ─ ─ Modular Design Coding Style and comprehensive before and after simulation Data interface design Finite state machine coding techniques and precautions Do the Distributed RAM encountered a few do not quite understand the signal Source Insight is compatible with VHDL and Verilog How to achieve signal delay? [Reserved] novice learning skills
Platform: | Size: 491520 | Author: 江风 | Hits:
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